1. Field of the Invention
The present invention relates to a transfer pulse generator circuit and an image pickup apparatus. More particularly, the present invention relates to a transfer pulse generator circuit for generating vertical register transfer pulses for driving vertical registers of a charge coupled device (CCD) type solid state image pickup device, and an image pickup apparatus equipped with a CCD type solid state image pickup device having the transfer pulse generator circuit.
2. Description of Related Art
In an image pickup apparatus equipped with a CCD type solid state image pickup device, charges accumulated in each light reception element provided in a light reception part of the CCD type solid state image pickup device are transferred to a vertical register, the charges transferred to each vertical register are transferred to a horizontal register, and the charges transferred to the horizontal register are transferred to an output circuit. An output from the output circuit is image information.
A period constituting one screen of a video device such as a display and a TV is called one frame. In the interlace system, for example, two fields constitute one frame.
Image information of one field or one frame is repetitively output so that images can be viewed on a video device as still images or moving images.
When charges are transferred in the horizontal register, the horizontal register is driven in a state that the operations of vertical registers are stopped, to extract charge information of one horizontal line (e.g., refer to FIG. 3 of Japanese Patent Application Publication No. 2000-138943). Pixel information on one frame can be transferred basically by outputting charge information on one horizontal line by a plurality of times corresponding to the number of horizontal lines.
Specifically, as shown in a timing chart of FIG. 5, vertical register transfer is performed during a horizontal blanking period (period indicated by a symbol b in the drawing) while a horizontal register transfer pulse indicated by a symbol Hck in the drawing holds a constant level (high level in the timing chart of FIG. 5), in order to avoid adverse effects of switching pulses of vertical register transfer pulses indicated by a symbol Vφ (Vφ1 to Vφ6) during an effective pixel period (period indicated by a symbol a.
Namely, a potential variation of a substrate formed with a CCD type solid state image pickup device occurs at vertical register transfer pulse fall timings (timings indicated by symbols T2, T4, T6, T8, T10 and T12 in the drawing) and at vertical register transfer pulse rise timings (timings indicated by symbols T1, T3, T5, T7, T9, and T11 in the drawing). In order to avoid an adverse effect of this potential variation upon an output from the output circuit, the vertical register transfer is performed during the horizontal blanking period. FIG. 6 is a graph showing a relation between the vertical register transfer pulse Vφ and a potential of a substrate on which a CCD type solid state image pickup device is formed. It can be seen from this graph that when a vertical register transfer pulse falls at a pulse through rate of 40 V/μs, the potential of the substrate formed with the CCD type solid state image pickup device changes by about 16 mV.
FIG. 7 is a schematic diagram showing a timing generator equipped with a conventional transfer pulse generator circuit. A timing generator 101 shown in the drawing is constituted of: a horizontal direction counter 102 which starts counting synchronously with a fall of a horizontal sync signal HD; PRM_OFFSET which stores a count (Ta value) of the horizontal direction counter from the fall timing of the horizontal sync signal HD to a timing indicated by a symbol T1 in FIG. 5; a comparator 103 which compares the count of the horizontal direction counter and the Ta value and outputs a reference signal when the count of the horizontal direction counter reaches the Ta value; and a Vφ generator 104 which generates a Vφ pulse by using the reference signal output from the comparator as a trigger.
The Vφ generator is equipped with a T counter 105, and is structured in such a manner that when the timing indicated by T1 is identified by the reference signal output from the comparator, the T counter counts timings indicated by T2 to T12 to identify them. Namely, the T counter provided in the Vφ generator operates in such a manner that Vφ pulses can be generated at the timings indicated by T2 to T12 without instructing the Vφ generator externally, by making the Vφ generator know only the timing indicated by T1 by using the reference signal.
In the timing generator constructed as above, by using the fall of the horizontal sync signal HD which is a signal externally input, as a reference, the horizontal direction counter starts counting. When the count of the horizontal direction counter reaches the Ta value (e.g., count 100) stored in PRM_OFFSET, the comparator outputs the reference signal. By using the reference signal output from the comparator as a trigger, the Vφ generator generates each pulse of Vφ1 to Vφ6, so that the vertical register transfer pulses of one horizontal line shown in FIG. 5 can be obtained. One horizontal transfer and corresponding one vertical transfer (period a+period b) are called a vertical transfer period.
Pixel information on one frame is transferred as the same vertical transfer period is transferred a plurality of times corresponding to the number of horizontal pixels (although a variety of transfer modes such as pixel thinning are used recently, these are not included).
The number of pixels of a CCD type solid state image pickup device is increasing nowadays because of market need for high image quality. Need for acquiring a number of images at the same time in a short time are also increasing. It is desired to realize a frame rate near a conventional frame rate also for a CCD type solid image pickup device having a large number of pixels.
A method of realizing a frame rate near a conventional frame rate also for a CCD type solid image pickup device having a large number of pixels may be: (1) a method of raising a drive frequency at which a CCD type solid state image pickup device is driven; and (2) a method of performing a vertical register transfer during an effective pixel period.
However, if a frame rate near a conventional frame rate is realized by raising the drive frequency at which a CCD type solid state image pickup device is driven, a rise in the drive frequency may cause an increase in a calorific power, an increase in a power consumption, high cost of a substrate formed with a CCD type solid state image pickup device, an increase in the number of peripheral components and the like. It is therefore difficult to say that the method of raising a drive frequency at which a CCD type solid state image pickup device is driven, to realize a frame rate near a conventional frame rate, is proper. Further, if only the countermeasure of raising the drive frequency is used, a limit is approaching for the recent requirements for improving the frame rate.
If a frame rate near a conventional frame rate is realized by performing a vertical register transfer during an effective pixel period, there arises, as described earlier, adverse influence of switching noises of vertical register transfer pulses. Namely, a potential of a substrate formed with a CCD type solid state image pickup device changes at rise/fall timings of each vertical register transfer pulse, so that an output of the output circuit may be adversely affected and fixed pattern noises (FPN) may be generated.
Specifically, as shown in a timing chart shown in FIG. 8, as a vertical register transfer is performed during an effective pixel period (period indicated by a symbol a in the drawing), a potential of the substrate formed with a CCD type solid state image pickup device changes: at a rise timing T1 of a vertical register transfer pulse indicated by a symbol Vφ6; at a fall timing T2 of a vertical register transfer pulse indicated by a symbol Vφ2; at a rise timing T3 of a vertical register transfer pulse indicated by a symbol Vφ1; at a fall timing T4 of a vertical register transfer pulse indicated by a symbol Vφ3; at a rise timing T5 of a vertical register transfer pulse indicated by a symbol Vφ2; at a fall timing T6 of a vertical register transfer pulse indicated by a symbol Vφ4; at a rise timing T7 of a vertical register transfer pulse indicated by a symbol Vφ3; at a fall timing T8 of a vertical register transfer pulse indicated by a symbol Vφ5; at a rise timing T9 of a vertical register transfer pulse indicated by a symbol Vφ4; at a fall timing T10 of a vertical register transfer pulse indicated by a symbol Vφ6; at a rise timing T11 of a vertical register transfer pulse indicated by a symbol Vφ5; and at a fall timing T12 of a vertical register transfer pulse indicated by a symbol Vφ1. This potential change may generate FPN at each of the change timings T1 to T12.
FPNs generated at respective change timings T1 to T12 are coupled vertically, and vertical linear image noises such as shown in FIG. 9A appear. FIG. 12 shows an actual image obtained by driving a CCD type solid state image pickup device in accordance with the timing chart shown in FIG. 7. Similar to FIG. 9A, it can be known from FIG. 12 that vertical linear image noises appear which are caused by FPNs generated at respective change timings T1 to T12.
Consider similar mechanism for a spot noise on the screens between frames and between fields. Image noises appear always at the same position between frames or fields. Therefore, a certain spot on the screen becomes always noises (dark or bright). These noises are spot noises staying resident on the screen irrespective of generation of vertical linear image noises.
Although these are two independent phenomena, the generation mechanism is the same in FPN and continuity (continuity of linear noises in the vertical transfer period, continuity of spot noises between frames or fields), so that if linear noises and spot noises are generated at the same time, the linear noises always appear on the screen.
Vertical register transfer pulses shown in FIG. 8 can be generated in a manner similar to that for the vertical register transfer pulses shown in FIG. 5. Namely, by using the timing generator shown in FIG. 7, the vertical register transfer pulses shown in FIG. 8 can be generated.